High Speed Switching Circuit Configuration

ABSTRACT

A low inductance electrical switching circuit arrangement, includes a two sided substrate with a plurality of through-substrate electrical vias. A capacitor is arranged on the substrate first side above a first via, and an electrical sink is arranged on the first side above a second via. A switching component configured to produce a plurality of current pulses is arranged on the substrate second side below the first and second via.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Patent Application Ser. No. 62/752,460, filed Oct. 30, 2018, entitled “High Speed Switching Circuit Configuration,” which is incorporated by reference herein in its entirety.

FIELD OF THE INVENTION

The present invention relates to electronic circuitry, and more particularly, is related to a high speed switching circuit.

BACKGROUND OF THE INVENTION

FIG. 1A shows a basic switching circuit 100 where an electronic switch 116 having a drain D and a source S is connected across a load (or sink 114), to a capacitor 112. The capacitor 112 may be charged via a connection CA. Access to the capacitor 112 herein is represented through the connection CA. Presently, circuit layouts for such circuits are inadequate for a switching circuit 100 to produce pulses meeting specific amplitude and time duration specifications. The physical layout of the circuit elements affects the performance when producing fast high current pulses, for example, having a pulse width of a ten nanoseconds or shorter duration and an amplitude of more than one amp. Incorrect layout, in particular excessive electrical lead line distances between components increases inductance and/or resistance in a current loop 180 shown in FIG. 1B, decreasing the maximum current that can flow through the circuit 100 and increasing the pulse width (duration). Therefore, there is a need in the industry to address the abovementioned shortcomings.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a high speed switching circuit configuration and method for producing the same. Briefly described, the present invention is directed to a low inductance electrical switching circuit arrangement with a two sided substrate with a plurality of through-substrate electrical vias. A capacitor is arranged on the substrate first side above a first via, and an electrical sink is arranged on the first side above a second via. A switching component configured to produce a plurality of current pulses is arranged on the substrate second side below the first and second via.

Other systems, methods and features of the present invention will be or become apparent to one having ordinary skill in the art upon examining the following drawings and detailed description. It is intended that all such additional systems, methods, and features be included in this description, be within the scope of the present invention and protected by the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principals of the invention.

FIG. 1A is a circuit diagram of a switching circuit.

FIG. 1B shows the circuit diagram of the switching circuit of FIG. 1A indicating a current loop.

FIG. 2A is a schematic diagram of a circuit layout for a first embodiment of a switching circuit from a side view.

FIG. 2B is a detail of the switching circuit 200 of FIG. 2A showing a current loop.

FIG. 3A is a schematic diagram of a circuit layout for a second embodiment of a switching circuit from a side view.

FIG. 3B is a schematic diagram of the circuit layout for the second embodiment of FIG. 3A indicating a surface mount package portion.

FIG. 4 is a schematic diagram of a circuit layout for a third embodiment of a switching circuit from a side view.

FIG. 5 is a schematic diagram of a circuit layout for a fourth embodiment of a switching circuit from a side view.

FIG. 6 is a circuit diagram of the first embodiment showing an array of capacitors and loads.

FIG. 7 is a flowchart of an exemplary first embodiment of a method for arranging a low inductance electrical switching circuit.

DETAILED DESCRIPTION

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

As used within this disclosure, a “lateral” or “horizontal” current path refers to a direction of current along the surface of a circuit board, for example through circuit board traces. A “vertical” current path refers to a direction of current substantially normal to the surface of a circuit board, for example, a current path traveling through a circuit board from a circuit board top surface to a circuit board bottom surface using a through via. As used herein, “substantially” means “very nearly,” or within typical manufacturing tolerances.

As noted in the background section above, FIG. 1A is a prior art circuit diagram of a switching circuit with components including the capacitor 112, the sink 114 (a laser diode), and the switch 116 (a FET switching element). The switch 116 has a terminal 118 (G) for input a trigger pulse to turn the switch 116 on, and CA access to the capacitor 112 to allow the capacitor 112 to be charged to a voltage level. While FIG. 1A depicts the electronic switch 116 by a symbol for a FET having a source (S), drain (D) and a gate (G), any electronic switch can be used that has similar function, namely input, output, and trigger terminals.

FIG. 2A is a schematic diagram showing an exemplary embodiment of a switching circuit 200 from a side view. A substrate 202, for example but not limited to, a printed circuit board (PCB), is configured to support circuit components on a first side 204, and on a second side 206 opposite the first side 204. The first side 204 and the second side 206 are separated by a substrate thickness 208, for example less than 1000 μm, preferably less than 500 μm, and ideally less than 175 μm. The substrate 202 includes at least two through-substrate electrical vias 220, 222 oriented substantially normal to the substrate 202. FIG. 2A shows a first via 220 with a first central axis 260 extending from the first side 204 through the substrate 202 to the second side 206 and a second via 222 with a second central axis 262 extending from the first side 204 to the second side 206. Each via 220, 222 may provide a first electrical contact point on the first side 204 and a second electrical contact on the second side 206, such that a first component on the first side 204 having an electrical connection to the first electrical contact is electrically connected to a second component on the second side 206 having an electrical connection to the second electrical contact. Such an electrical connection may have considerably lower inductance than a typical (longer) electrical connection, for example laterally electrically connecting components via a wire bond connection or circuit board trace. FIG. 2A does not depict the first/second electrical contact of the vias 220, 222 for clarity, instead showing electrical connections directly to the vias 220, 222.

A capacitor 212 has electrical connections, such as a first capacitor wire bond pad 274 and the second capacitor wire bond pad 275 on a first side of the sink 214, and a circuit board connector 232 on a second side of the capacitor 212. The wire bond pads 274 and 275 may be electrically connected. For example, the wire bond pads 274, 275 may be different areas of a larger pad. Alternative embodiments may use different types of electrical connections, for example, a metal tab, among other possibilities. The capacitor 212 has a thickness 209, for example less than 1000 μm, preferably less than 500 μm, and ideally less than 175 μm. The capacitor 212 is arranged to attach to the substrate 202 on the substrate first side 204, for example, via a solder connection between the capacitor circuit board connector 232 and the first via 220. Note that while FIG. 2A shows the capacitor circuit board connector 232 being relatively thick for visual clarity, generally the capacitor circuit board connector may be very thin, for example a thin trace or foil of a conductive metal.

A switching component 216 configured to produce a plurality of current pulses is arranged to be attached on the second side 206 of the substrate 202. The switching component 216 may be electrically connected to the capacitor 212 through the via 220 using a gate electrical contact 238 on the switching component 216. While FIG. 2A shows a single drain electrical contact 238 for simplicity, the drain electrical contact 238 may be implemented with one, two or more physical electrical contacts. Arranging the switching component 216 directly opposite the capacitor 212 through the substrate 202 provides a very short connection length between the capacitor 212 and the switching component 216, reducing both resistance and inductance that might otherwise be introduced using lateral electrical connections in conventional one sided circuit boards, for example, circuit board traces and/or wire bonds.

An electrical sink 214, for example a laser diode or laser diode array, has an electrical connection, such as a sink wire bond pad 276 on a first side of the sink 214, and a circuit board connector 234 on a second side of the sink 214. Alternative embodiments may use different types of electrical connections, for example, a metal tab, among other possibilities. The sink 214 is arranged on the first side 204 of the substrate 202 with the sink circuit board connector 234 adjacent to and in electrical communication with a second via 222 electrically connecting the sink 214 to the source contact 238 on the switching component 216 through the substrate 202. The switching component 216 may be electrically connected to the sink 214 through the via 222 using a source electrical contact 236 on the switching component 216. While FIG. 2A shows a single source electrical contact 236 for simplicity, the source electrical contact 236 may be implemented with one, two or more physical electrical contacts. The gate and trigger signal of the switching component 216 are not shown in the drawings for purposes of clarity. It should be noted that while the description of the current path circuit above is somewhat simplified for purposes of clarity, the full path is described below.

While, as shown in FIG. 2A, the electrical sink 214 may have the same thickness 209 as the capacitor 212, in alternative embodiments the electrical sink 214 may be thicker or thinner than the capacitor 212.

While FIG. 2A shows a single first via 220 connecting the capacitor 212 on the first side 204 of the substrate 202 to the switching component 216 on the second side 206 of the substrate 202, two or more first vias 220 may be used to increase the electrical and thermal conductivity and reduce the inductance between the first 206 and second sides of the substrate 202. Likewise, there may be more than one second via 222 connecting the switching component 216 with the sink 214. One or more wire bonds 226 may be used for electrically connecting the capacitor 212 with the electrical sink 214 via the second capacitor wire bond pad 275 on the capacitor 212 and the electrical sink wire bond pad 276 on the electrical sink 214. Alternative embodiments may use different types of electrical connections, for example, a metal tab, among other possibilities.

By reducing the length of interconnects between the switching component 216, the capacitor 212, and the sink 214, pulse generation characteristics may be improved. Under the first embodiment, a current loop 280 (FIG. 2B) through the electrical connections between the capacitor 212, switching component 216 and the sink 214 may have a total inductance level below 5 nanohenries. The inductances of each interconnect are preferred to be less than 5 nanohenries, preferably under one nanohenry each, even more preferably under one nanohenry total. An accumulated length of electrical connections of the current loop 280 (FIG. 2B) between the capacitor 212, switching component 216 and the sink 214 is preferably less than 5 mm. Each of the interconnect lengths is less than 5 mm in length, preferably less than 1 mm in length. For example, an interconnect length may be as small as 10 μm in length when the interconnect is a bond line of conductive material, such as solder or conductive epoxy. By such improvements in the interconnects, pulses having a current amplitude of at least one amp and a pulse duration of less than 1 nanosecond may be achieved.

The arrangement of the switching component 216, capacitor 212 and sink 214 with respect to two sides 204, 206 of the substrate 202 is leveraged to minimize interconnection lengths. The gate and trigger signal of the switching component 216 are not shown in the drawings for purposes of clarity. FIG. 2B is a detail of the switching circuit 200 of FIG. 2A showing the current loop 280 as a dark line. Under the first embodiment, the current loop 280 through the capacitor 212, the electrical sink 214, and the switching component 216 does not traverse lateral electrical pathways/traces on either surface of the substrate 202. The current loop 280 is shown as starting at the capacitor 212, traversing the sink 214, the substrate 202, the switching component 216, the substrate 202 again, and ending at the capacitor 212. Including the connecting components, the current loop 280 traverses elements 212-275-226-276-214-234-222-236-216-238-220-232-212. The arrangement of the circuit 200 significantly reduces inductance in the current loop 280 over previous circuit arrangements incorporating lateral current paths on a surface of a circuit board. As shown in FIG. 2A, each of the of vias 220, 222 has an axis 260, 262 substantially normal to the substrate 202. By arranging each of the capacitor 212 and the switching component 216 to intersect with the first via axis 260, the electrical interconnection between the capacitor 212 and the switching component 216 may be made without any lateral connections (such as wire bonds or traces) across the faces of the first substrate side 204 and/or the second substrate side 206. Similarly, by arranging each of the sink 214 and the switching component 216 to intersect with the second via axis 262, the electrical interconnection between the sink 214 and the switching component 216 may be made without any lateral connections across the faces of the first substrate side 204 and/or the second substrate side 206.

Additional circuit elements may also be included in the circuit 200, for example, a capacitor charging element 230 may be attached to the substrate 202 first side 204 and electrically connected to the capacitor 212, for example, via a wire bond connection 224 between a second charging element wire bond pad 273 to the first capacitor wire bond pad 274, or alternatively via traces on the substrate (not shown). Alternative embodiments may include more than one charging element 230, for example, embodiments with an array of capacitors/loads, Other circuit elements, for example, a controller 250 may be incorporated into the circuit 200 in a similar fashion, such as, via a wire bond connection 240 between a first charging element wire bond pad 272 to a controller wire bond pad 271.

The inductance added by the electrical connections 240, 224 between the controller, 250, the capacitor charging element 230, and the capacitor 212 does not detract from the pulse generation performance of the current loop 280. It may be preferable for the wire bond connection 224 between the additional circuit elements 230, 250 and the capacitor 212 to have a higher inductance with respect to the current loop 280 to help isolate the electrical parasitics of the additional circuit elements 230, 250 from the current loop 280.

It should be noted that while the embodiments described herein are based on the circuit of FIG. 1A, various modifications are possible. For example, the order and electrical orientation of the components 112, 114, and/or 116 as implemented in the embodiments may differ from the circuit arrangement shown in FIG. 1A and, for example, the switch 116 may be any type of electronic switch. Likewise, while FIG. 2A shows a single switch circuit, similar configurations may be implemented for an array of switch circuits. For example, the capacitor 212 of FIG. 1 may be replaced with a circuit 600 (FIG. 6) having an array of capacitors and/or sinks, for example, for use in multi-channel switches. The controller 250 (FIG. 2A) may be configured to control which capacitor 112 (FIG. 6) is charged, and thus which load channel receives the pulse current.

While in general the capacitance value for a channel may be adjusted by using several capacitors wired together, such arrangements may undesirably increase the inductance in the circuit, degrading the performance. Therefore, it may be desirable to use as few capacitors as possible, and instead of combining several capacitors together using a single capacitor that may have its capacitance parameters adjusted by adjusting the physical dimensions of the capacitor. For example, a sequence of individual capacitors chained together may be replaced by a single capacitor that is dimensionally specified, for example by length, to the desired electrical characteristics. Specifically, this may be used to tailor the capacitance of a switching circuit without introducing an undesirable increase in inductance.

FIG. 3A is a schematic diagram of a circuit layout for a second embodiment 300 of a switching circuit from a side view. Under the second embodiment 300, a first substrate 301 and a second substrate 302 are arranged back-to-back, with through vias 320 connecting the two circuit boards 301, 302 and providing electrical connections between first circuit board components 312, 314 on the front face of the first circuit board 301 and second circuit board components 316, 318 on the front face of the second circuit board 302 while, like the first embodiment 200, minimizing lateral connections between components 312, 314, 316, where 312 and 314 have top and bottom contacts and 316 having contacts on one side. For example, the first circuit board components may include a capacitor 312 and laser diode (sink) 314, and the second circuit board components may include a chip resistor 318 and a switch 316. FIG. 3A shows via contact pads 325 providing electrical connection surfaces on the front/back surfaces of the circuit boards 301, 302 to the through vias 320. Electrical connections between component top surfaces may be made by wire bonds 324, 326. Solder 328 may provide electrical connections between component bottom surfaces and the via contact pads 325. Likewise the via contact pads 325 of the first circuit board 301 and the second circuit board 302 may be electrically connected with solder 328.

While the first substrate 301 may be a circuit board, alternatively, as shown by FIG. 3B the first substrate may include a leadframe 395 for a leadframe style surface mount package 390, indicated by the dash-dot line. Here, the capacitor 312 and the sink 314 are mounted to the leadframe floor (the first substrate 301) in the surface mount package 390, with leadframe lands 395 providing electrically conductive surfaces for top and bottom electrical contact pads of the package 390, where the top pads provide electrical contacts to the capacitor 312 and the sink 314, and the bottom pads provide electrical contacts to the second substrate 302, for example, a substrate 302. The leadframe lands 395 provide electrical conductivity between the top and bottom of the first substrate 301 in lieu of through vias 320, where leadframe contact pads 396, for example a metallization layer, may serve as electrical contact surfaces analogous to the via contact pads 325. The surface mount package 390 may be, for example but not limited to, quad-flat no-leads (QFN) or dual-flat no-leads (DFN) packages.

FIG. 4 is a schematic diagram of a circuit layout for a third embodiment 400 of a switching circuit from a side view. The third embodiment has each of components 312, 314, 318, 316 mounted to one of two surfaces of a component substrate 202 similar to the two sided substrate 202 of the first embodiment. Under the third embodiment 400, the capacitor 312 and sink 314 are mounted on opposite sides of the component substrate 202 from the switch 316 as with the first embodiment 200, with electrical connections for a current loop 480 made through substrate vias 320. The third embodiment adds a thermally conductive substrate 404 mounted back to back with the component substrate 202 beneath the sink 314, with through vias 320 in both the component substrate 202 and the thermally conductive substrate 404 to convey heat from the sink 314 to a heat sink 450 mounted on the front face of the thermally conductive substrate 404, while still minimizing lateral electrical connections. A thermal conductor and electrical insulator 329 disposed between the component substrate 202 and the thermally conductive substrate 404 provides a thermal conduit between the component substrate 202 and the thermally conductive substrate 404, while not providing an electrical conduit between the component substrate 202 and the thermally conductive substrate 404. Alternatively the substrate 404 and electrical insulator 329 may be replaced by a single thermally conductive component formed of any material that is not electrically conductive. Alternately heat sink 450 may be made from thermally conductive but electrically non-conductive material in which case the electrical insulator is not required but still can be used.

FIG. 5 is a schematic diagram of a circuit layout for a fourth embodiment 500 of a switching circuit from a side view. The fourth embodiment 500 is similar to the third embodiment 400. Like the third embodiment, first side components 312, 314, are mounted on a first surface of a two sided substrate 202, and second side components 316, 318, are mounted on a second surface of the two sided substrate 202. In contrast with the third embodiment 400, the thermally conductive substrate 404 of the third embodiment 400 is not used, but instead a heat sink 550 is arranged physically so it can thermally attach to the two sided substrate 202 by way of the thermal conductor and electrical insulator 329. Like the third embodiment, heat is conveyed from the sink 314 to the heat sink 550 by through vias 320 in the substrate 202, while still minimizing lateral electrical connections.

In alternative embodiments, the heat sink 550 may be made from thermally conductive but electrically non-conductive material, for example, where the electrical insulator is not required.

Under some operating conditions the sink 314 may run hot. The component arrangement of the first and second embodiments may result in the through vias 320 conducting heat between the switch 316 and the sink 314. The third embodiment and a fourth embodiment, described above, are include heat sinks 404, 505 to provide thermal cooling for the sink 314 and to reduce thermal conductivity between the sink 314 and the switch 316. A trade-off for this arrangement is the addition of a (preferably) short lateral current path 460 along the substrate 202 to convey current between the sink 314 and the switch 316.

FIG. 7 is a flowchart 700 of an exemplary first embodiment of a method for arranging a low inductance electrical switching circuit. It should be noted that any process descriptions or blocks in flowcharts should be understood as representing modules, segments, portions of code, or steps that include one or more instructions for implementing specific logical functions in the process, and alternative implementations are included within the scope of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention. The method is described here with reference to the low inductance electrical switching circuit arrangement (200) shown in FIG. 2.

A two sided substrate (202) is provided, as shown by block 710. The substrate has a plurality of through-substrate electrical vias (220, 222) oriented substantially normal to the substrate first and second sides, each via having a first electrical contact disposed on the first side electrically connected through the substrate to a second electrical contact disposed on the second side opposite the first electrical contact. A capacitor (212) is attached to the first side of the substrate with a capacitor circuit board connector adjacent to and in electrical communication with a first via (220), as shown by block 720. An electrical sink (214) is attached to the first side of the substrate with the sink circuit board connector adjacent to and in electrical communication with a second via (222), as shown by block 730. A switching component (216) is attached to the second side of the substrate adjacent to and in electrical communication with the first via, as shown by block 740. In some embodiments, the switching component is also adjacent to and in electrical communication with the second via.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents. 

We claim:
 1. A low inductance electrical switching circuit arrangement, comprising: a substrate further comprising: a first side; a second side opposite the first side and separated from the first side by a substrate thickness; and a plurality of through-substrate electrical vias oriented substantially normal to the substrate first side and second side, each via further comprising a first electrical contact disposed on the first side electrically connected through the substrate to a second electrical contact disposed on the second side opposite the first electrical contact; a capacitor comprising a first side electrical contact on a capacitor first side and a circuit board connector on a capacitor second side, the capacitor arranged on the first side of the substrate with the capacitor circuit board connector adjacent to and in electrical communication with a first via; an electrical sink comprising a first side electrical contact on a sink first side and a circuit board connector on a sink second side, the sink arranged on the first side of the substrate with the sink circuit board connector adjacent to and in electrical communication with a second via; and a switching component configured to produce a plurality of current pulses arranged on the second side of the substrate adjacent to and in electrical communication with the first via.
 2. The circuit of claim 1, wherein the switching component is arranged on the second side of the substrate adjacent to and in electrical communication with the first via and the second via.
 3. The circuit of claim 1, wherein the capacitor is configured to discharge current pulses through the switch and the sink.
 4. The circuit of claim 1, further comprising a conducting element configured to electrically connect the capacitor first side electrical contact to the sink first side electrical contact.
 5. The circuit of claim 4, wherein a current loop comprising the electrical connections between the capacitor, switching component and the sink has a total inductance level below 5 nH.
 6. The circuit of claim 4, wherein a current loop comprising an accumulated length of electrical connections between the capacitor, switching component and the sink is less than 5 mm.
 7. The circuit of claim 1, wherein: each of the plurality of vias has an axis substantially normal to the substrate first side and second side; the capacitor and the switching component intersect with the first via axis; the switching component intersect with the first and/or second via axis; and the sink components intersect with the second via axis.
 8. The circuit of claim 1, wherein the substrate comprises a printed circuit board.
 9. The circuit of claim 1, further comprising a heat sink comprising a heat transfer surface arranged in thermal communication with the second via on the substrate second side opposite the electrical sink.
 10. A method for arranging a low inductance electrical switching circuit, comprising: providing a substrate further comprising: a first side; a second side opposite the first side; and a plurality of through-substrate electrical vias oriented substantially normal to the substrate first side and second side, each via further comprising a first electrical contact disposed on the first side electrically connected through the substrate to a second electrical contact disposed on the second side opposite the first electrical contact; attaching a capacitor to the first side of the substrate with a capacitor circuit board connector adjacent to and in electrical communication with a first via; attaching an electrical sink to the first side of the substrate with a sink circuit board connector adjacent to and in electrical communication with first and a second via; and attaching a switching component to the second side of the substrate adjacent to and in electrical communication with the first via.
 11. The method of claim 10, wherein the switching component is further in electrical communication with the second via.
 12. The method of claim 10, further comprising the step of attaching a heat sink comprising a heat transfer surface arranged in thermal communication with the second via on the substrate second side opposite the electrical sink.
 13. A low inductance electrical switching circuit arrangement, comprising: a first substrate and a second substrate, each further comprising: a first side; a second side opposite the first side and separated from the first side by a substrate thickness; and a plurality of through-substrate electrical vias oriented substantially normal to the substrate first side and second side, each via further comprising a first electrical contact disposed on the first side electrically connected through the substrate to a second electrical contact disposed on the second side opposite the first electrical contact; the first substrate and the second substrate arranged back to back with the first substrate second side adjacent to the second substrate second side; a capacitor arranged on the first side of the first substrate adjacent to and in electrical communication with a first circuit board first via; an electrical sink arranged on the first side of the first substrate adjacent to and in electrical communication with a second via; and a switching component configured to produce a plurality of current pulses arranged on the first side of the second substrate adjacent to and in electrical communication with the first via and the second via, wherein the first substrate first via is arranged adjacent to and in electrical communication with the second substrate first via, the first substrate second via is arranged adjacent to and in electrical communication with the second substrate second via, the first and second circuit board first vias and the first and second circuit board second vias arranged to provide a vertical current path from the switching component to the electrical sink and the capacitor to the switching component.
 14. The low inductance electrical switching circuit arrangement of claim 13, further comprising: a leadframe style surface mount package comprising a leadframe, wherein the first substrate comprises the leadframe, and the electrical sink and the capacitor are mounted to the leadframe and are in electrical and thermal communication with the leadframe.
 15. The low inductance electrical switching circuit arrangement of claim 14, wherein the second substrate comprises a printed circuit board, and the a leadframe style surface mount package is mounted to the printed circuit board. 